Enough to drop samples, so its probably more to do with my PIO program, I will look into more when I have time.I see, but can do more than that
How much jitter are we talking about? Also delay?
Many different DACs, from old R-2R chips, some ESS chips, AKM, all the way to my custom FPGA DACs. I wanted this to be universal. The jitter is a problem even when the DAC has input reclock (all of them do have at least flip-flops to sync to their internal clock domain) as it modulates the silicon substrate and gets all the way to the DAC outputs in many cases. ADAU17xx, PCM51xx... all of them use PLLs, which work well for the performance they are claiming... You never see PLLs in high-end DACs.Thinking again, what DAC are you using ? There are some Analog Devices (ADAU17xx??) devices with internal DSPs which recreate the clock and data cleanly from a messy input. As long as there aren't too many or not enough samples, the jitter disappears.
The solution seem to be to tune my PIO to resync every frame and then have D flip-flops externally to attenuate the jitter. I had to do something similar with SAM3U back in the day...
Thanks for the feedback, now its clear that thats the only realistic way.
Statistics: Posted by dohny — Sun Jan 11, 2026 7:23 pm