The BCM2711 data sheet mentions wait cycles the DMA can carry out before and after each write:
p. 42 DMA.TI register:
I could guess the DMA has a clock frequency and it is the number of clock cycles that are being waited. So what is the clock frequency of the DMA? Or what is the clock frequency relevant for the DMA cycles?
I know that the WAITS field cannot be used to accurately time DMA transfers, but I just need a certain minimum delay in a DMA CB chain. That could perhaps be fulfilled with the WAITS field, if one would know what the unit is.
As a bonus question, when do the waits happen? Just on read or on write, or both? If both, the total delay would be twice the amount specified in WAITS.
The DMA4 by the way has two fields S_WAITS and D_WAITS where one individually can control the waiting for read and write (p. 53). This may be an indication the the plain DMA just does on read and write.
p. 42 DMA.TI register:
But there is no mention on how long these cycles are.25:21. WAITS Add Wait Cycles
This slows down the DMA throughput by setting the
number of dummy cycles burnt after each DMA read or
write operation is completed.
A value of 0 means that no wait cycles are to be added.
I could guess the DMA has a clock frequency and it is the number of clock cycles that are being waited. So what is the clock frequency of the DMA? Or what is the clock frequency relevant for the DMA cycles?
I know that the WAITS field cannot be used to accurately time DMA transfers, but I just need a certain minimum delay in a DMA CB chain. That could perhaps be fulfilled with the WAITS field, if one would know what the unit is.
As a bonus question, when do the waits happen? Just on read or on write, or both? If both, the total delay would be twice the amount specified in WAITS.
The DMA4 by the way has two fields S_WAITS and D_WAITS where one individually can control the waiting for read and write (p. 53). This may be an indication the the plain DMA just does on read and write.
Statistics: Posted by aha4242 — Sun Nov 16, 2025 8:30 am