ARM is little endian and IO is big endian. Network order is big endian. htons should do the trick. However using a 16-bit transfer should do this for you automatically. (If not using the channel bswap setting should resolve it.)
DMA is a CMT coprocessor with limits. I would be tempted to manage as much as possible on the CPU. So htons moving down the stack. By the time DMA sees it there is no real concern.
Mixing little and big is a fun. There are some interpreter tricks with little on the CPU. (The register file is big.) However IO generally benefits from complete words which implies big. This leads to mixed memory domains. If they wanted to they could create conventions in memory addresses, but I doubt that will ever happen. If anything the understanding of the RAM is little. So DMA should be able to understand little to big based on word size in flight. Little only appears in certain cases such as the interpretation of pointers. (Aka casting.) Most of the system is big most of the time.
General advice use proper types and type translators. (C++?) In this case use 16-bit transfers.
DMA is a CMT coprocessor with limits. I would be tempted to manage as much as possible on the CPU. So htons moving down the stack. By the time DMA sees it there is no real concern.
Mixing little and big is a fun. There are some interpreter tricks with little on the CPU. (The register file is big.) However IO generally benefits from complete words which implies big. This leads to mixed memory domains. If they wanted to they could create conventions in memory addresses, but I doubt that will ever happen. If anything the understanding of the RAM is little. So DMA should be able to understand little to big based on word size in flight. Little only appears in certain cases such as the interpretation of pointers. (Aka casting.) Most of the system is big most of the time.
General advice use proper types and type translators. (C++?) In this case use 16-bit transfers.
Statistics: Posted by dthacher — Sat Nov 16, 2024 10:21 am
