Let's address the concerns.
With the new chip, I am using intensively the debugging interface (SWD at 10 MHz) which is some sort of SPI, bidirectional on same data line wit pull-ups, also the both UARTs. All of them are using the same type of pads, and they are working just fine.
BTW Tested with slight overclock (400 MHz) and the signal looks somehow ... better.
Also generated 200 MHz burst from SIO, almost clean square, level transitions start to defy my poor oscilloscope's sampling rate (1Gs/s). I was really concerned about this, not anymore.
With the new chip, I am using intensively the debugging interface (SWD at 10 MHz) which is some sort of SPI, bidirectional on same data line wit pull-ups, also the both UARTs. All of them are using the same type of pads, and they are working just fine.
BTW Tested with slight overclock (400 MHz) and the signal looks somehow ... better.
Also generated 200 MHz burst from SIO, almost clean square, level transitions start to defy my poor oscilloscope's sampling rate (1Gs/s). I was really concerned about this, not anymore.
Statistics: Posted by gmx — Sat Sep 07, 2024 10:55 pm