Note there may be a way to get atomic enable via CTRL_TRIG in RP2040, if the event system is different. This would allow 2D arrays to be used as a linked list. (They do not have true linked list support, but you can make something close to it.) If bit zero of the CTRL_TRIG is set to zero the transfer descriptor belongs to the CPU, if set to one it belongs to the DMA. This is synchronous and allows async behavior. These control transfers create overhead.
The exact behavior of the event system is not clear to me. (Note this is not the previously mentioned bullet list.)
The design of the DMA in RP2040 is very CPU centric. I suspect this was intentional, however in RP2350 we saw something different. It makes me curious if 2D arrays and chaining are not fully supported. We are responsible for forcing a join.
So looking through the features in the registers for possible issues. Most of the features are optional and support their own control flow. However I found a few which do not seem to have any control flow.
The exact behavior of the event system is not clear to me. (Note this is not the previously mentioned bullet list.)
- Error exceptions do not raise interrupts or abort/pause?
- RP2040, no comment
- RP2350, small comment
- DMA writing to control trigger with bit zero clear while channel is disabled does what?
- I should get an interrupt in this case regardless of IRQ quiet.
- However I am not sure DMA has any way of knowing that. (It would just stop without warning?)
- In theory these modes in RP2350 should be able to fix that. (I am not sure they did.)
- On RP2040, I would need to get an interrupt after every completed control transfer.
- However I am not sure DMA has any way of knowing that. (It would just stop without warning?)
- I should get an interrupt in this case regardless of IRQ quiet.
- DMA writing to transfer count upper bits with illegal value does what?
- Done for binary compatibility and to keep the 4 main registers?
- Seems to me there would be more events which register an interrupt
- Null trigger
- RP2040 supported
- RP2350 supported
- Completion
- RP2040 supported
- RP2350 supported
- Illegal trigger
- Illegal mode (RP2350 only)
- Error
- RP2350 supported
- Null trigger
The design of the DMA in RP2040 is very CPU centric. I suspect this was intentional, however in RP2350 we saw something different. It makes me curious if 2D arrays and chaining are not fully supported. We are responsible for forcing a join.
So looking through the features in the registers for possible issues. Most of the features are optional and support their own control flow. However I found a few which do not seem to have any control flow.
Statistics: Posted by dthacher — Wed Aug 28, 2024 8:45 pm
