Yeah, they don't really bother to specify the platform-level stuff, it's unfortunate.Many thanks. I had never found anything which definitively said where RISC-V execution should start so my own code generating tools assume the start of RAM or Flash and places a 'j _power_on_reset' there which then initialises the SP.
On Hazard3 there is just a constant parameter on the cores for the first address to fetch instructions after reset. On RP2350 this is set to 0x7dfc, the highest address in ROM except for the 512-byte Arm SG region at the very top. RISC-V enters the top of the ROM, Arm enters the bottom, and they figure stuff out in the middle.
I did a survey of embedded RISC-V runtimes and found that the most common behaviour is to expect the image to be entered at its lowest address, so that is the ROM's behaviour when you don't have an explicit entry point specified. This means SDK binaries always have an explicit entry point item, because we match the code layout between Arm and RISC-V.
Statistics: Posted by LukeW — Thu Aug 22, 2024 8:29 pm
