No Slaves were connected with the above capture. Just 1k ohm resistors to 3.3V. Nice sharp edges on the scope (can't see that in the logic analyzer capture). I used both my RP2040 XIAO and Pico boards (identical results).that initial value looks to be a reset default, its configured for 6.5mhz!Code:
IC_FS_SCL_HCNT_1 is 6IC_FS_SCL_LCNT_1 is 13and now with this, its configured for 399,361HzCode:
IC_FS_SCL_HCNT_1 is 126IC_FS_SCL_LCNT_1 is 187
thats assuming a 125mhz clk_sys
if you unplug all i2c slaves, what does the logic analyzer say?
I added the reading of the CLK_SYS_DIV register before and after, and no change there (125MHz before and after). Either documentation is incorrect or there is a hardware bug.
Code:
CLOCKS_BASE = 0x40008000CLK_SYS_DIV = CLOCKS_BASE + 0x40print("CLK_SYS_DIV_INT is {:d}".format((mem32[CLK_SYS_DIV] & 0xFFFFFF00)>>8)) # bits [31:8] are INT divprint("CLK_SYS_DIV_FRAC is {:d}".format((mem32[CLK_SYS_DIV] & 0x000000FF))) # bits [8:0] are Fractional divCode:
CLK_SYS_DIV_INT is 1CLK_SYS_DIV_FRAC is 0Statistics: Posted by chipace — Sat Mar 16, 2024 5:24 pm